1. Technical Field
The present disclosure relates to an amplification stage associated with an output pad of an integrated circuit chip formed inside and on top of a substrate of semiconductor-on-insulator type.
2. Description of the Related Art
FIG. 1 is an electric diagram of an example of an amplification stage associated with an output pad of an integrated circuit chip. The amplification stage receives, on an input terminal IN, a data signal DINT generated by circuits (not shown) of the chip, and delivers, on an output terminal OUT connected to an output pad (not shown) of the chip, a signal DEXT capable of being exploited outside of the chip. Signal DINT is a digital signal capable of alternating between a high value and a low value. Signal DEXT follows the variations of signal DINT, but at a higher voltage level, and with a power and an impedance adapted to a connection to an external device. The high and low values of signal DINT substantially correspond to respective high and low voltages VDDI and GNDI for powering the logic circuits of the chip. The high and low values of signal DEXT substantially correspond to respective high and low voltages VDDE and GNDE for powering the output stages of the chip. As an example, voltages VDDI and GNDI respectively are on the order of 1.2 V and 0 V, and voltages VDDE and GNDE respectively are on the order of 2.5 V and 0 V.
The output amplification stage comprises a pre-amplification stage 1 and a power and impedance matching stage 3. Stage 3 comprises a P-channel MOS power transistor 5, in series with an N-channel MOS power transistor 7. The sources of transistors 5 and 7 are respectively connected to high (VDDE) and low (GNDE) power supply rails, and the drains of transistors 5 and 7 are connected to node OUT. Thus, when transistors 5 and 7 are respectively on and off, node OUT is at a voltage close to VDDE, and when transistors 5 and 7 are respectively off and on, node OUT is at a voltage close to GNDE. Transistors 5 and 7 are selected to provide a power and an impedance adapted to an exploitation of signal DEXT outside of the chip.
Pre-amplification stage 1 receives signal DINT, and provides a control signal DP to the gate of transistor 5 and a control signal DN to the gate of transistor 7. Stage 1 comprises a first branch between terminal IN and the gate of transistor 5, providing signal DP, and a second branch between terminal IN and the gate of transistor 7, providing signal DN. Each branch comprises a voltage step-up circuit, respectively 9P and 9N, capable of converting signal DINT into an intermediary signal of same shape but pre-amplified to voltage level VDDE, GNDE. Circuits 11P and 11N are respectively provided between the output of circuit 9P and the gate of transistor 5, and between the output of circuit 9N and the gate of transistor 7, to control the rising and falling edges of the pre-amplified intermediary signal. The function of circuits 11P and 11N especially is to prevent the possibility for transistors 5 and 7 to be turned on at the same time during the switching, which would result in short-circuiting the output stage power supply. As an example, the falling edges of signal DP may be slightly delayed with respect to the falling edges of signal DN, and the rising edges of signal DN may be slightly delayed with respect to the rising edges of signal DP. Further, circuits 11P and 11N operate as inverters, that is, signals DP and DN are in phase opposition with respect to signal DINT. Since the power and impedance matching stage (transistors 5 and 7) itself operates as an inverter, this enables for signal DEXT to be in phase with signal DINT.
An amplification stage associated with an output pad of an integrated circuit chip formed inside and on top of a substrate of semiconductor-on-insulator type is here considered. Such a substrate, generally called SOI, comprises an active semiconductor layer, for example, an epitaxial silicon layer, coating an insulating layer. In SOI technology, it can be selected from among two types of transistors, transistors with a floating bulk and transistors having a bulk capable of being biased via a contacting area.
FIGS. 2A to 2C schematically show an N-channel MOS transistor 20, with a floating bulk, formed in an SOI-type substrate. FIG. 2A is a top view, FIG. 2B is a cross-section view along axis B-B, and FIG. 2C is a cross-section view along axis C-C.
Transistor 20 is formed inside and on top of a P-type semiconductor region 21 coating an insulating layer 22. Transistor 20 takes up, in top view, an approximately rectangular surface area delimited by vertical insulating walls 23. The well formed by layer 22 and walls 23 fully insulates transistor 20 from the other chip components. N-type regions 24 and 25, forming the source (S) and the drain (D) of the transistor, extend longitudinally on either side of an insulating layer 26, formed at the surface of region 21 and coated with a conductive gate 27 (G). Metallizations (not shown) may be provided on the source and drain regions. No contacting is provided to bias bulk 21 (B), which thus remains floating.
FIGS. 3A to 3C schematically show an N-channel MOS transistor 30, formed in an SOI-type substrate having a bulk capable of being biased via a contacting area. FIG. 3A is a top view, FIG. 3B is a cross-section view along axis B-B, and FIG. 3C is a cross-section view along axis C-C.
Transistor 30 is formed inside and on top of a P-type semiconductor region 31 coating an insulating layer 32. Transistor 30 takes up, in top view, an approximately rectangular surface area delimited by vertical insulating walls 33. N-type regions 34 and 35, forming the source (S) and the drain (D) of the transistor, extend longitudinally on either side of an insulating layer 36 coated with a conductive gate 37 (G). A heavily-doped P-type region 38 is formed in the upper part of a portion of region 31 which is not coated with gate 37. Region 38 enables to bias bulk 31 (B) of the transistor to a desired reference voltage. Region 38 may be coated with a contact metallization (not shown).
It has been suggested to form an output amplification stage of the type described in relation with FIG. 1, in which transistors 5 and 7 of the power and impedance matching stage are floating-bulk transistors. Floating-bulk transistors have the advantage of having shorter switching times. Indeed, since the bulk region is not connected to a reference voltage, electric charges are capable of building up therein. In an N-channel transistor, the building up of such positive charges results in increasing the voltage of the bulk region, and thus in decreasing the threshold voltage of the transistor. This results in faster switchings of the transistor when signal DN switches state. Similarly, in a P-channel transistor, negative charges tend to build up in the bulk region, thus resulting in faster switchings when signal DP switches state.
The use of transistors with a floating bulk however has several disadvantages. A first disadvantage is the history effect due to the lack of biasing of the bulk. At a given time, the bulk voltage partly depends on the on or off states successively taken by the transistor at previous times. Thus, the threshold voltage of the transistor fluctuates according to the states taken by the data signal at previous times. As a result, even though switching times are short, they are subject to a strong dispersion. A second disadvantage is that the building up of charges in the bulk region increases leakage currents when the transistor is off. In particular, in an N-channel transistor, the building up of positive charges in the bulk region results in forward biasing the junction formed between the bulk and the source. As an example, a positive voltage of a few tenths of a volt may settle between the bulk and the source. This results in non-negligible leakage currents, causing an unwanted increase in the static consumption of the output stage. The same phenomenon (with inverted biasings) occurs in a P-channel transistor.
It has been provided to form an amplification stage of the type described in relation with FIG. 1, in which transistors 5 and 7 are provided with a bulk contacting area, the bulk of transistor 5 being connected to high reference voltage VDDE, and the bulk of transistor 7 being connected to low reference voltage GNDE. This enables to overcome the above-mentioned disadvantages of off-state leakage currents and of switching time dispersion. However, the advantage of a fast switching due to the building up of electric charges in the bulk region is then lost.
It would be desirable to have an output stage in which power amplification transistors have switching times which are both short and with a small dispersion, as well as decreased leakage currents.